Senior/Junior ASIC design CAD engineer

职责简介：
 
AMD CAD team负责AMD 产品（APU，独立显卡等）研发使用的ASIC design flow的实现，设计和维护。ASIC design flow是实现从RTL到网表（AMD称为front-end flow），从网表到GDSII（AMD称为back-end flow 或者Physical Design flow）的自动化流程。AMD ASIC design flow是基于业界领先EDA工具包括Synopsys, Cadence，Mentor等，由多种脚本语言设计的高度自动化和标准化的流程。
 
要求：
1.     计算机，微电子或者相关专业，有一定的工作经验或者研发经验。
2.     熟悉数字电路前端（synthesis,  formal verification）或者后端设计（Floorplan, place, CTS, route, STA, Library, etc.）。
3.     熟悉Linux操作系统的使用。
4.     熟悉一种或者多种编程或者脚本语言（CShell, TCL, Perl, Python等）优先。
5.     了解一种或者多种数字电路设计的EDA工具优先。
6.     英语基础好，口语流利，写作好。
7.     求知欲强，综合分析问题能力强，喜欢编程写脚本。
 
DESCRIPTION OF DUTIES:
 
1.     Participate in the design and implementation of the leading edge, front-end or back-end ASIC design flow which covers from logical design to physical implementation
2.     Participate in the research of Design Methodology to improve automation and  productivity
3.     Work closely with design team for projects’ Tapeout
 
PREFERRED EXPERIENCE:
1.     Major in CS, EE or related, master or bachelor degree.
2.     Knowledge of ASIC design (Digital circuit design, verilogHDL) is required
3.     Be familiar with Linux working environment
4.     Experience in program with one or more languages (CShell, TCL, Perl or python etc.) is a plus
5.     Experience in any ASIC flow and/or EDA tools is a plus
6.     Good in English writing and speaking
7.     Be eager to learn new knowledge, be able to resolve complex problem.