数字后端产品测试工程师
- 12万-18万/年
- 上海
- |
- 工作经验不限
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,五险一金,福利好,成长空间大
发布时间: 2017-01-09发布
职位描述
Position Description:
1.Validate EDA software in ASIC design flow;
2.Responsible for developing, applying, and maintaining quality standards for complex EDA software system;
3.In charge of our daily yellow process quality;
4.Be responsible for full QA weekend launching.
Position Requirements:
1.The candidate should have basic knowledge of HDL(Verilog preferred) and microelectronics.
2.Knowledge of IC DESIGN flow is highly preferable;
3.Previous experience of ASIC design (Cadence/Synopsys/Magma platforms) is highly preferable;
4.Candidate must possess good Chinese and English communication skills;
5.Candidate must have demonstrated strong problem solving skills, ability to work on large software systems;
6.Highly motivated and passion to work is required. Detail focusing, performance oriented;
Major in EE/CS, and all level of experiences are welcomed. BS is preferred.
职位发布者
Cadence
HR
简历处理用时
简历及时处理率
Cadence
领域: 移动手持,消费电子,通信网络
规模: 500-1000人
主页: http://www.cadence.com.cn/
工作地址:
上海,芳甸路1155号,浦东嘉里中心
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