哎呀,这个职位已经下线啦
加特兰微电子科技(上海)有限公司
Senior IC Layout Engineer
- 12万-18万/年
- 上海
- |
- 3年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,五险一金,福利好,老板nice,年底双薪,股票期权,成长空间大,技术领先
发布时间: 2017-01-17发布
职位描述
Job description
As a Senior IC Layout Engineer at Calterah Semiconductor, he/she will be responsible for layout and physical verification of key analog and RF blocks in advanced CMOS technology nodes. He/she will work with IC team to meet scheduled deadlines, performing layout, verification and final GDS preparation of the entire IC.
Responsibilities
· Full custom analog layout/verification and RC extraction.
· Perform block and top level layout. Conduct physical verification (DRC and LVS using Cadence tools).
· Team work with analog designers, optimize layout.
· Prepare LEF for digital PR and integrate PR blocks into SoC.
· Prepare GDS database for tapeout.
Skills required
- 3+ years experiences in CMOS analog/RF/mixed-signal block layout.
- Experience in mass production CMOS wireless chip layout.
- Familiar with layout skills and Cadence CAD tools.
- Familiar with advanced CMOS nodes 65nm/40nm/28nm.
- Able to work with digital team to achieve final SoC integration.
- Good teamwork/communication/positive is must.
Education
Bachelor required;
职位发布者
Vivi Yang
HR
7天
简历处理用时
93%