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硅谷数模半导体(北京)有限公司

版图设计工程师(Layout Design Engineer)

  • 18万-24万/年
  • 北京
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,老板nice,技术领先,成长空间大,技能培训

发布时间: 2020-09-20发布

职位描述

Job Description:
1.Work with circuit designers to build physical design floor-plan; 
2.Complete the physical layout design with the constraints of circuit design
  requirements; 
3.Verify the physical layout design to meet both circuit design requirements and process
  requirements; 
4.Use the advanced technologies to improve layout design quality and efficiency. 

Requirements:
1.College degree (or above) in Electrical Engineering or other related engineering field;
2.At least 4 years experience in layout design field with rich tapeout experience; 
3.Good understanding of basic electronic principles dealing with circuit and layout design; 
4.Familiar with IC layout methodologies, flows and CAD tools such as Cadence virtuoso layout
  and caliber physical verification; 
5.Prefer experienced in PLL and high speed IO design; 
6.Patient, a good team player, good communication skills. 

◆ We provide competitive compensation & benefit package as well as ample opportunities for professional development. Salary negotiable

职位发布者

theresa

HR

7天

简历处理用时

96%

简历及时处理率