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ASR

Senior/staff ASIC Implementation Engineer

收藏职位
  • 我要分享
  • 24万-42万/年
  • 上海
  • |
  • 1-3年
  • |
  • 本科
  • |
  • 全职

职位诱惑: 五险一金,福利好,老板nice,十五薪,成长空间大

发布时间: 2019-12-10发布

职位描述

Job Description:
- Block, IP macro or SoC level implementation in 28nm or 16nm TSMC process
- UPF Synthesis with Synopsys DC or DCT/G flows
- Full Chip formal check on RTL2Gate and Gate2Gate with LEC and/or formality tools.
- Full Chip CLP check with CPF for nonPG and PG netlists for low power signoff.
- Working with BE team to timing closure in Primetime-SI on multi-corners and multi-modes
- Ability to build or perfect the EDA-methodology-flow with perl, tcl or shell
- Knowledge on DFT (mbist/scan) will be an added advantage

Qualifications:
- BSEE degree or above
- Strong understanding of synthesis flow using DC/DCT/DCG - for a low power (UPF) and
high speed- complex SoC
- Hands on experience with formal verification tools such as LEC and/or formality
- Must have the CTS conceptions in ICC at P&R stage
- Strong STA skills. Must have thorough knowledge on closing timing at unit and top level
- Experience in mbist and scan will be plus
- Proficient in Perl, Tcl and Shell programming
-Good team work spirit

职位发布者

ASR HR

VP

7天

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100%

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