ASIC Design Verification Engineer

Responsibilities:

• Understand the ASIC design/verification flow and help design/verification engineers to accomplish targets.
• Develop infrastructure and environment for IP/SoC level design verification.
• Closely working with Design/Architecture/Verification team to develop new verification component.

• Major in Electrical Engineering, Computer Science or related
• Good understanding on ASIC design verification flow
• Good design verification experience
• Programming knowledge on Verilog/SystemVerilog, C/C++
• Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
• Should have good communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
• Strong problem solving skills