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Cadence

Lead Application Engineer-DIP

  • 24万-30万/年
  • 上海
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 补充公积金 补充医疗保险 五险一金

发布时间: 2017-01-09发布

职位描述

Position Description:
1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications
2) Interface with customer architects and IP business unit to enable evaluation of application specific IP performance and features per customer’s SoC requirements.
3) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships
4) Providing customer feedback on new/existing requirements for Design IP usage from customers to the R&D business unit
5) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SoC
6) Writing application notes and review protocol specifications for Design IP

Position Requirements:
1) Experience in SoC design
2) Good understanding of SoC architecture
2) Experience with DDR subsystem hardware or firmware testing or debugging
3) Good understanding DDR protocols and knowledgeable for DDR IP
4) Good written and verbal communication skills and problem solving skills are required
5) Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team
6) Travel within AP region may be required.
7) Good understanding of the semiconductor IP marketplace and ecosystem is a plus

职位发布者

Cadence

7天

简历处理用时

70%

简历及时处理率

Cadence

Cadence

领域: 移动手持,消费电子,通信网络

规模: 500-1000人

主页: http://www.cadence.com.cn/

工作地址:

上海,芳甸路1155号,浦东嘉里中心

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