Lead Design Engineer-Memory Modeling Portfolio

Position Description:
1. Responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardware based verification products.
2. Also responsible for updating, maintaining, documenting, and supporting existing system level memory model products.
3. Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP.
4. Interface with internal and external customers to work on diverse problems and solutions related to emulation, simulation, or verification.
5. Perform as team member toward cross verification of and cross training in memory IP as well as in developing and using lifecycle processes to ensure product quality.
  
Position Requirements:
Essential:
1. The position requires BSEE, or equivalent, with a minimum of 4 yrs of industry experience in designing hardware systems.
2. RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.
3. Experience with team-wide collaboration tools and process. Drive and ability to schedule workload and plan own tasks effectively.
4. Must have excellent communication skills with both written and spoken English.

Strongly Recommended:
1. Verification experience using Cadence simulation and/or emulation products is highly desired.
2. Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended.
3. Experience in memory sub-system design and operation is strongly recommended.