高级硬件工程师-数字前端验证

Position Description:
He/she will be member of a team of advanced field engineers who deploy and support advanced hardware based verification flow integration technical engagements and provide easy-to-adopt packages and workshops to Cadence field application engineers and customers alike.
He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers:
(1) Cadence Palladium HW Acceleration Platforms
(2) Cadence Acceleratable Verification IP portfolio
(3) HSV product integration with other Cadence products such as Incisive Simulation and/or Joules for power analysis
(4) HW/SW Co-verification solutions for SoC designs
HW based verification experience such as other emulators or FPGA prototyping based verification is required
Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments.
We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW co-design and co-verification.
The person should possess team-success orientation, mature work attitude, and good judgment under pressure.

Position Requirements:
- Minimum Education Required: education level of BS with 7+ years’ experience (or MS with 10+ or more years’ experience).
- A good knowledge of RTL design and verification tools (HDLs, synthesis tools, design simulation, acceleration using emulators)
- Knowledge of the needs of SoC design and verification
- Knowledge of UNIX, C/C++, other scripting programming languages (Perl, TCL…) is highly desired
- Strong verbal and written communication skills in English are required
- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must
- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must.