Lead/Senior Design Engineer-数字前端
- 18万-24万/年
- 上海
- |
- 5年以上
- |
- 本科
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- 全职
职位诱惑: 五险一金 补充医疗保险 补充公积金 员工旅游 餐饮补贴 通讯补贴 绩效奖金 股票期权 定期体检 弹性工作
发布时间: 2017-01-09发布
职位描述
Position Description:
Deliver/implement DDR IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.
Specific duties include:
- Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow
- Proficiency in logic design, simulation, synthesis, STA and testing
- Proficiency in Verilog and its simulation environment
- Good knowledge of IC design
* At least five years experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
Position Requirements:
1. Essential Qualifications: Must have BS degree with 6+ years of applicable experience, MS degree with 4+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written. 3. Requires good communication skills in English.
职位发布者
Cadence
简历处理用时
简历及时处理率
Cadence
领域: 移动手持,消费电子,通信网络
规模: 500-1000人
主页: http://www.cadence.com.cn/
工作地址:
上海,芳甸路1155号,浦东嘉里中心
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