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Cadence

高级软件开发工程师-逻辑综合

  • 18万-24万/年
  • 上海
  • |
  • 3年以上
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 五险一金 股票期权 专业培训 定期体检 补充医疗保险

发布时间: 2017-01-09发布

职位描述

Position Description:
1. Responsible for development and maintenance of the synthesizer for Palladium.
2. Implementation for new VHDL/Verilog feature support in synthesizer.
3. Logic optimization and performance improvement in synthesizer.

Position Requirements:
1. MS above in CS/EE or similar level of expertise with 3+ years of working experience.
2. Be skilled in C/C++ programming on Linux platform.
3. Good team player with strong written and verbal communication skills.
4. Familiar with VHDL/Verilog and knowledge on EDA tools of simulation, synthesis is required.
5. Familiar with the distributed computing and database development is preferred.
 

职位发布者

Cadence

HR

7天

简历处理用时

69%

简历及时处理率

Cadence

Cadence

领域: 移动手持,消费电子,通信网络

规模: 500-1000人

主页: http://www.cadence.com.cn/

工作地址:

上海,芳甸路1155号,浦东嘉里中心

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