ASIC设计

Senior  ASIC  Design Engineer
Job description
l   Be responsible for the development of digital circuit design in SoC or Mixed Signal products.
l   Define internal design spec basing on marketing datasheet
l   Responsible for RTL design & simulation, logic synthesis, static timing analysis, formal check and DFT.
l   Support FPGA verification
l   Support product test and debug after sample release.
 
Qualification Requirements
l   Bachelor degree or above in EE
l   Minimum 3 years ASIC logic design experience
l   Familiar with HDL design with Verilog or VHDL
l   Familiar with ASIC/SoC design and verification flow
l   Familiar with the ISO/IEC 14443 tape A and type B is a plus.
l   Familiar with scripts of TCL, Perl, etc. is a plus.
l   Familiar with Place & Routing flow is a plus.
l   A successful product development from specification to GDSII experience is a plus
l   Good communication skills and teamwork
 
高级ASIC设计工程师
主要职责：
l  负责SoC或混合信号芯片中数字电路的RTL设计开发工作
l  负责设计文档的撰写
l  负责逻辑综合，静态时序分析，一致性验证等
l  参与测试和仿真向量生成，FPGA相关验证支持
l  参与芯片的样品调试和量产测试.
任职资格：
l  硕士学历，电子工程，微电子，或相关专业
l  3年以上数字电路设计经验
l  熟悉ASIC 流程，熟悉VHDL/Verilog
l  具有通信、数字、模拟电路的基础知识，学习能力强；
l  良好的沟通能力及团队合作精神
l  有成功产品完整开发和流片经历, 尤其智能卡或RFID领域, 优先考虑.