#25963 Sr. ASIC/ Layout Design Engineer-SOC DFT/DFX

RESPONSIBILITIES:

• Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
• Perform verification on all DFT structures
• Generate DFT related timing constraints and work with PD team for timing closure
• Generate and verify DFT structural patterns and functional patterns
• Participate in ATE bring-up and debug the DFT patterns on ATE
• Design and implement other DFX (debug, characterization, yield etc) logics

• Familiar with Unix/Linux environment and good at scripts
• Understand the architecture of the chip and functional block being designed
• Build C/C++ model for simulation
• Build test bench and monitors for DUT
• Compose test plan and validation vectors to ensure functional completeness
• Debug function/performance bugs of graphics chips
• Preferred Experience:
• Familiar with Linux Environment (including shell scripting and linux gnu tools)
• Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
• Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification
• Should have excellent communication skills (both written and oral)
• Strong problem solving skills

• Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences