ASIC/SOC Physical Design-数字后端

Responsibility:

1. Gate level- synthesis / logic equivalency checking / timing optimization / layout, for high speed logic designs using standard cell libraries in the most recent technology nodes
2. Floor planning / placement and routing
3. Design constraint optimization
4. Clock tree synthesis, useful clock skew insertion, clock uncertainty & critical paths specification
5. Fluency in Cadence Encounter Tools environment
6. Power domain partitioning, power grid layout & dynamic voltage drop  / decap analysis
7. Perform SI / crosstalk analysis with regard to timing impact
8. Perform both static and dynamic IR drop analysis with regard to timing impact
9. Run test vectors / simulations to exercise timing critical segments of the design
10. Integration of hard and soft IP macros / blocks into SoC
11. ECO generation
12. LVS / DRC / physical design signoff
13. Support device GDSII database delivery and checking at major ASIC foundries
14. Design and tapeout experience of 28nm
15. Packaging technology and process