可测性设计工程师

12万-24万/年
上海
|
3年以上
|
本科
|
全职

职位诱惑: 五险一金商业保险公积金绩效奖金节日礼物弹性工作定期体检年度旅游技能培训生育补贴子女福利外派津贴带薪年假团队聚餐

发布时间: 2016-06-02发布

职位描述

Responsibilities:
1.Participate in SoC level DFT architecture definition.
2.Implement DFT strategy for the SoC chips, cooperating with design team
3.Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
4.Develop the high coverage and cost effective test patterns.
5.Verify all DFT logics and test patterns with simulation and static timing analysis tool.
6.Support other teams for DFT related problems.
Requirements:
1.Either Bachelor or Master degree, 2+ years related experience required.
2.Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA
3.Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG.
4.Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools
5.Proficient in Verilog/VHDL language
6.Be familiar with Shell/TCL/Perl program, or skilled in C program
7.Good English communication skills
8.Self-motivated and good team player