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大唐恩智浦半导体有限公司

Validation Engineer

收藏职位
  • 我要分享
  • 18万-30万/年
  • 上海
  • |
  • 工作经验不限
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,成长空间大

发布时间: 2018-07-12发布

职位描述

1. Position Title:    Validation Engineer
To define the FPGA development plan according to the requirement from design or software team
Porting internal ASIC design to FPGA platform
To setup FPGA simulation environment
To mentor junior validation engineers in FPGA development
To define pre-silicon or post-silicon validation test plan and do resource estimation
To create and execute validation test for both pre-silicon and post-silicon validation
To report validation result to management team
Qualification Requirement
1. BS/MS in electrical/computer engineering with 3+ years of experience in FPGA development
2. Familiar with Xilinx device structure & synplicity tools (synplify_premier, identify, certify) & Xilinx PAR tools
3. Experienced in FPGA design & simulation environment setup
4. A good understanding of the FPGA timing, FPGA clocking
5. Must be proficient in Verilog HDL
6. Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
7. Working knowledge in C/C++, Makefile
8. Big plus with experience in USB 2.0 or Ethernet
9. Big plus with experience in ARM M0, M0+ and M4 based MCU
10. Big plus with experience in IAR and CodeWarrior debugger Tool
11. Fluent English (both written and spoken) and excellent communication skills.

职位发布者

datang nxp

HR

7天

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