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矽昆微电子

IC验证工程师

收藏职位
  • 我要分享
  • 18万-30万/年
  • 上海
  • |
  • 工作经验不限
  • |
  • 学历不限
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,老板nice,技术领先

发布时间: 2019-01-02发布

职位描述

(Senior) ASIC verification Engineer  
Job Description:
The verification tasks include block level, chip level verification, test plan creation, scripting, coverage, regression run etc..

Requirements:
The candidate is preferred to be MSEE with minimum of 3+ years, in digital ASIC/SOC design verification. More experience will be considered as senior engineer or lead.

The candidate should have good understanding on ASIC/SOC design flow and should have:
0. Familiar with one of major verification languages: UVM, C, C++, SystemVerilog, Verilog 
1. Good knowledge of design verification methodology, such as UVM or OVM and coverage driven verification methodology
2. Many experiences with simulation model creation and the testbench build
3. Strong RTL coding with Verilog and familiar with front-end design flow
4. Background in one of the area below will be a strong plus:
a. Strong C/C++ software development experiences for ARM based SoC system
b. Video, display, GPU, DDR, PCIe, USB etc..
5. Be familiar with scripting language, such as Perl, C shell, Makefile.

职位发布者

矽昆微电子

ASIC

7天

简历处理用时

100%

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