哎呀,这个职位已经下线啦
北京华芯通半导体技术有限公司
Staff Design Implementation Engineer(面议)
- 18万-36万/年
- 北京
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,五险一金,福利好,成长空间大
发布时间: 2018-04-12发布
职位描述
- Location
Beijing/Shanghai - Responsibilities
1. Responsible for digital logic synthesis, STA, formal verification and low power check
2. Responsible to develop timing constraint and low power design constraint
3. Responsible to co-work with physical design team for timing closure
4. Responsible to optimize digital frontend flow qualification - Qualifications
Education and Experience
1. Major in CS, EE or related, BSEE required, MSEE preferred
2. 5+ years of hands-on experience in design implementation related field
Skills and Knowledge
1. Strong knowledge of digital logic design, synthesis, STA, formal verification, etc.
2. Strong experience with Design compiler, Prime time and Formality/Conformal LEC
3. Knowledge of DFT or physical design is a plus
4. Familiar with common UNIX utility such as Shell, Perl, TCL
5. Good English communication skills
6. Self-motivated and good team player
职位发布者
刘强
7天
简历处理用时
96%