哎呀,这个职位已经下线啦
北京华芯通半导体技术有限公司
Senior Layout Design Engineer(面议)
- 1.2万-2.4万/年
- 北京
- |
- 3年以上
- |
- 本科
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- 全职
职位诱惑: 年终奖金,五险一金,福利好,成长空间大
发布时间: 2018-12-26发布
职位描述
- Location
Beijing/Shanghai - Position Description
1. Work with circuit designers to build physical design floorplan.|2. Complete the high performance physical layout design.|3. Verify and improve the physical layout design.|4. Help junior layout engineer study quickly. - Responsibilities
- Qualifications
1. Bachelor degree (or above) in Electrical Engineering or other related engineering field.
2. At least 4 years’ experience in layout design field with rich tapeout experience.
3. Good understanding of basic electronic principles dealing with circuit and layout design.
4. Familiar with IC layout methodologies, flows and EDA tools such as Cadence virtuoso layout and caliber physical verification.
5. Prefer experienced in memory and standard cell library design.
6. Patient, a good team player, good communication skills.
7. English language skill in writing is a must.
职位发布者
刘强
7天
简历处理用时
98%