Senior IP verification engineer（面议）

职位诱惑: 年终奖金,五险一金,福利好,成长空间大

发布时间: 2018-09-29发布

Location
Beijing/Shanghai
Position Description
Finish the verification tasks of the specific IPs which assigned by the IP DV team leader in time and in high quality
Responsibilities
1. Create the testplan and reviewed with the team leader and designer
2. Create the random constraint testbench based on the requirement
3. Create the random testcase and the direct testcase to cover the IP design feature
4. Debug the testbench and RTL, and report the bug to designer
5. Finish the verification tasks in time
Qualifications
1. Education and Experience
2. Bachelor or above with 3 years work experience
Skills and Knowledge
1. System Verilog
2. UVM
3. C++ is an additional plus
4. Formal verification experience is an additional plus
5. PCIE/SATA/USB/Ethernet/SPI/I2C/etc experience is an additional plus

7天

92%

领域: 消费电子,智能硬件,安全标签

规模: 200-500人

工作地址:

北京

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