IP Verification Engineer（面议）

职位诱惑: 年终奖金,五险一金,福利好,成长空间大

发布时间: 2018-12-26发布

Location
Beijing/Shanghai
Position Description
finish the verification tasks of the specific IPs which assigned by the IP DV team leader in time and in high quality
Responsibilities
1. Create the testplan and reviewed with the team leader and designer
2. Create the random constraint testbench based on the requirement
3. Create the random testcase and the direct testcase to cover the IP design feature
4. Debug the testbench and RTL, and report the bug to designer
5. Finish the verification tasks in time
Qualifications
Education and Experience
Bachelor or above
Skills and Knowledge
System Verilog
UVM
C++ is an additional plus
Formal verification experience is an additional plus
PCIE/SATA/USB/Ethernet/SPI/I2C/etc experience is an additional plus