哎呀,这个职位已经下线啦
北京华芯通半导体技术有限公司
Chip Level PV Engineer(面议)
- 1.2万-2.4万/年
- 北京
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- 3年以上
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- 本科
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- 全职
职位诱惑: 年终奖金,福利好,五险一金,成长空间大
发布时间: 2018-12-26发布
职位描述
- Location
Shanghai / Beijing - Position Description
Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Work on physical design of deep sub-micron Server CPU chips top level (full chip) floorplanning, timing closure, place&route, physical verification etc. Especially focus on top level PV validation, including DRC/LVS/DFM. - Responsibilities
1. Work on top level physical implementation flow from RTL to post-route, and focus on top level PV validation, including DRC/LVS/DFM.
2. PV flow build: top level automatic PV flow build, including DRC/LVS/ANT/ERC/DFM flow.
3. PV check and fix: top level PV including DRC/LVS/ANT/ERC/DFM run. Quick debug and fix any PV issues. Try to prevent PV issues in early design stage.
4. Evaluate new EDA PV tools and PV methodology best-fitted for current project.
5. Evaluate new process feature based on current project, figure out new process impact on backend flow, and trace on any potential PV issues.
6. Help block engineers to solve PV issues. - Qualifications
Education and Experience
MSEE with 2+ years or Bachelor with 3+ years of industrial experience of deep submicron digital ASIC design
Skills and Knowledge
1. Good knowledge in following physical design concepts: synthesis, floorplan, place-and-route, timing closure, timing sign-off, DFT, power analysis, hierarchical flow
2. Skilled in the field of IC digital implementation flow and major EDA tools such as DC, ICC/ICC2, EDI/INNOVUS, PT, Redhawk or equivalent
3. Skilled in scripting and building flow automation using Tcl, Perl, Python or equivalent
4. Good listening, writing and speaking English
5. Good communication skills, strong interpersonal skills and the flexibility
6. Plus with 5+ projects tapeout experience
职位发布者
刘强
HR
7天
简历处理用时
97%