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北京华芯通半导体技术有限公司

Chip Level Power Engineer(面议)

  • 1.2万-2.4万/年
  • 北京
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,成长空间大

发布时间: 2018-12-26发布

职位描述

  • Location
    Shanghai / Beijing
  • Position Description
    Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Work on physical design of deep sub-micron Server CPU chips top level (full chip) floorplanning, timing closure, place&route, physical verification etc. Especially focus on top level Power analysis IR/EM (static and dynamic), power estimate (from early to late stage), power planning (power mesh define, UPF flow), Low power design.
  • Responsibilities
    1. Work on top level physical implementation flow from RTL to post-route, and focus on top level power part: top level Power analysis, power estimate, power planning, Low power design.
    2. Power planning: new process power network, PG strategy define.
    3. Power estimate: power estimate based on netlist & post layout, improve consistency between them.
    4. Power analysis: static & dynamic power analysis, chip IR/EM analysis, result fix.
    5. Low power design: Low power UPF flow build, low power backend implement.
    6. Evaluate new EDA Power tools and Power methodology best-fitted for current project.
    7. Evaluate new process feature based on current project, and help to figure out best power planning.
    8. Help block engineers to solve power issues.
  • Qualifications
    Education and Experience
    MSEE with 5+ years or Bachelor with 7+ years of industrial experience of deep submicron digital ASIC design
    Skills and Knowledge
    1. Good knowledge in following physical design concepts: synthesis, floorplan, place-and-route, timing closure, timing sign-off, DFT, power analysis, hierarchical flow
    2. Skilled in the field of IC digital implementation flow and major EDA tools such as DC, ICC/ICC2, EDI/INNOVUS, PT, Redhawk or equivalent
    3. Skilled in scripting and building flow automation using Tcl, Perl, Python or equivalent
    4. Good listening, writing and speaking English
    5. Good communication skills, strong interpersonal skills and the flexibility
    6. Plus with 5+ projects tapeout experience

职位发布者

刘强

7天

简历处理用时

97%

简历及时处理率

北京华芯通半导体技术有限公司

北京华芯通半导体技术有限公司

领域: 消费电子,智能硬件,安全标签

规模: 200-500人

主页: http://www.hxt-semitech.com

工作地址:

北京

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