ASIC Design Verification Engineer - DV 前端验证 Verilog

RESPONSIBILITIES:

• Verification of SoC level design using random methodologies
• Interface with global architecture and design teams, understand graphics SoC design and feature set
• Test Planning, Implementation and Execution.
• Develop System Verilog (UVM) or C/C++ testbench and verification components.
• Maintain and Interface with existing random generators, models and APIs
• Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.

• Have in depth knowledge and hands-on experience in complex SoC design and functional verification
• Expertise in UVM based verification methodology
• Proficiency in System Verilog, C or C++
• Expertise in Perl, Tcl or other scripting language
• Kwnoledge of graphics architecture is a plus.
• Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.
• Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
• Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
• Must have good communication & Analytical thinking skills.
• Should have proficiency in flow development and scripting.
• Should be able to provide Technical mentoring and guidance to junior engineers.

• Master with at least 3 years or Bachelor with at least 5 years working experience in ASIC area