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北京华芯通半导体技术有限公司

DDR IP Design Engineer (All levels)

  • 18万-36万/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,成长空间大

发布时间: 2018-09-29发布

职位描述

Description:
Design DDR controller and PHY, including specification, architecture, micro-architecture, implementation (using Verilog), and verification

Expected skills:

  • 2+ years hands-on experience
  • Programming skills in Verilog HDL
  • Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation)
  • Highly motivated and skillful at solving difficult technical problems
  • Knowledge of bus or low-power design techniques is a plus
  • Experience of DDR controller or PHY design is a plus

职位发布者

刘强

HR

7天

简历处理用时

92%

简历及时处理率