ASIC可测性设计
- 24万-48万/年
- 上海
- |
- 3年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,福利好,老板nice,节日礼物,技术领先
发布时间: 2017-04-14发布
职位描述
Chip DFT (Design for Test) Engineer
Location: Shanghai
DFT Engineer is responsible for the DFT design and verification of
ASIC chips, including test architecture definition, scan chain insertion, scan compression,
Memory BIST insertion, ATPG, test structure verification and etc. Capable to define and deliver
competitive DFT solution with optimized test cost, high test coverage, low test power and
short TAT.
Requirements:
1. ME/EE or background in related areas.
2. At least 2 years of industry working experience of chip DFT design and verification.
3. Solid experience using Mentor Tessent on Memory BIST insertion and verification is a
STRONG plus.
4. Proficient in Verilog/VHDL, and well conversant with programming and script languages.
5. Good English skills, communication skills, and willingness to work with a global team. Skill
in other languages is a plus.
6. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible
and dynamic environment.