Senior Physical design engineer 高级数字后端设计工程师
Handle all aspects of chip backend design, including floor planning, place and routing, CTS, timing convergence iterations/optimization, DFT and final DRC/LVS.
1. BSEE, MSEE or higher.
2. 2~4 years experience of large ASIC backend designs.
3. Experience with Synopsys and/or Cadence design tools.
4. Familiar with 45/40nm or lower CMOS process designs.
5. Having successful tape out experience will be a great plus.
6. Good communication skills, team spirit and be anxious to learn during daily work.