Senior Physical design engineer 高级数字后端设计工程师

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12万-24万/年
上海
|
1-3年
|
本科
|
全职

职位诱惑: 年终奖金,五险一金,老板nice,股票期权,技术领先,成长空间大,十八薪

发布时间: 2019-07-05发布

职位描述

Responsibilities：
Handle all aspects of chip backend design, including floor planning, place and routing, CTS, timing convergence iterations/optimization, DFT and final DRC/LVS.

Qualifications:
1. BSEE, MSEE or higher.
2. 2~4 years experience of large ASIC backend designs.
3. Experience with Synopsys and/or Cadence design tools.
4. Familiar with 45/40nm or lower CMOS process designs.
5. Having successful tape out experience will be a great plus.
6. Good communication skills, team spirit and be anxious to learn during daily work.