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北京华芯通半导体技术有限公司

Sr. Staff/Staff DFT Engineer

  • 24万-48万/年
  • 上海
  • |
  • 5年以上
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,技术领先,成长空间大

发布时间: 2018-12-26发布

职位描述

 Responsibilities
- Responsible for DFT planning regarding to IP or SoC
- Responsible for implementation and verification for MBIST
- Responsible for implementation and verification for Scan/ATPG
- Responsible for DFT pattern generation, release and ATE bring-up
- Responsible for DFT flow/quality improvements
 
Qualifications
Education and Experience
- Major in CS, EE or related, BSEE required, MSEE preferred
- 5+ years of hands-on experience in DFT related field
 
Skills and Knowledge
- Strong knowledge of DFT including scan, ATPG, BIST and other DFT methodology
- Strong experience with popular DFT EDA, Mentor DFT solution is preferred
- Knowledge of synthesis, STA is a plus
- Familiar with common UNIX utility such as Shell, Perl, TCL
- Good English communication skills
- Self-motivated and good team player

职位发布者

刘强

HR

7天

简历处理用时

97%

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