Staff/Sr.Staff Design Implementation Engineer
- 24万-48万/年
- 上海
- |
- 5年以上
- |
- 硕士
- |
- 全职
职位诱惑: 年终奖金,五险一金,福利好,老板nice,成长空间大,技术领先
发布时间: 2018-04-19发布
职位描述
Responsibilities
- Responsible for digital logic synthesis, STA, formal verification and low power check
- Responsible to develop timing constraint and low power design constraint
- Responsible to co-work with physical design team for timing closure
- Responsible to optimize digital frontend flow qualification
Qualifications
Education and Experience
- Major in CS, EE or related, BSEE required, MSEE preferred
- 5+ years of hands-on experience in design implementation related field
Skills and Knowledge
- Good knowledge of digital logic design, synthesis, STA, formal verification, etc.
- Good experience with Design compiler, Prime time and Formality/Conformal LEC
- Knowledge of DFT or physical design is a plus
- Familiar with common UNIX utility such as Shell, Perl, TCL
- Good English communication skills
- Self-motivated and good team player
职位发布者
刘强
HR
简历处理用时
简历及时处理率
北京华芯通半导体技术有限公司
领域: 消费电子,智能硬件,安全标签
规模: 200-500人
主页: http://www.hxt-semitech.com
工作地址:
上海市浦东新区祖冲之路2290号展想广场
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