验证工程师（Verification Engineer）

◆ We provide competitive compensation & benefit package as well as ample opportunities for professional development. Salary negotiable.

Job Description:
1.Understanding the expected functionality of designs;
2.Developing testing and regression plans;
3.Designing and developing verification environment;
4.Running RTL and gate-level simulations/regression;
5.Code/functional coverage development, analysis and closure;
6.Release the documents during the verification flow. Such as verification plan, usage of the verification environment, simulation result of test cases, verification coverage report, etc.
 
Requirements:
1.Minimum of 3 years design/verification experience (test plan, test bench, assertions,‎ debugging designs, code coverage etc.);
2.Knowledge in ASIC/FPGA design process and verification tools/env (UVM/OVM…);
3.Familiar with design and verification languages (Verilog, System Verilog, SVA etc.);
4.Scripting and automation skills (tcl, perl, makefile etc) a plus;
5.Familiar with C/C++;
6.Knowledge of high speed interface, such as DDR, DisplayPort, etc.
7.Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills, English and other foreign languages;
8.Independent and self-managing;
9.Cooperative and active in daily work.