MTS ASIC Design Engineer-Feint

收藏职位

30万-42万/年
上海
|
3年以上
|
本科
|
全职

职位诱惑: 年终奖金,五险一金,交通补助,免费班车,技能培训,成长空间大

发布时间: 2019-02-25发布

职位描述

Job Responsibilities:
-Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
-Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.

Job Requirements:
-Familiar with Verilog RTL design and has experience of large digital ASIC project.
-Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
-Familiar with unix/linux and scripts (tcl, perl etc.)
-Fluent English on talking, presentation and writing documents.
-Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.