Use DC (Design Compiler), ICC (IC Compiler) for chip synthesis with SDC either from RTL code or Gate level netlist. Cadence flow is welcome also.
Static Timing analysis and Formal verification
Perform timing analysis and timing optimization
Run formal verification after each ECO and timing optimization
Place & route, Physical verification
Knowledge about physical synthesis flow and floorplan; Familiar with place & route tools like encounter, ICC, Astro; Knowledge about process, DRC and LVS. Knowledge about DFM is better. Low power design knowledge is preferred.
DFT design: RTL coding; Scan chain insertion; JTAG/Boundary scan insertion; NAND tree insertion; Memory BIST insertion; Logic BIST insertion; Test pattern generation and simulation; ATPG test vector generation and pattern simulation; Fault grading test vector generation; Memory BIST simulation; JTAG/NAND tree simulation; Test vector format conversion and provide all test related patterns to test and product engineers
BS is basic, MS is preferred
§ Working Experience:
0-3 years working experience on chip integration or related experiences in back end design
§ Professional Knowledge:
Strong Logic design and Semiconductor device physic background
Good English in both written and spoken