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光梓信息科技(上海)有限公司

Digital/ASIC Design Engineer

收藏职位
  • 我要分享
  • 18万-24万/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,老板nice,股票期权,年度旅游,技术领先,成长空间大,技能培训

发布时间: 2019-07-05发布

职位描述

Job Description:
 

  1. This position is for a digital/ASIC design engineer to build next-generation analog/mixed-signal SoC chipsets.
  2. Handle many aspects of ASIC design flow including: architecture, RTL coding/Verification, Synthesis, DFT, STA and P&R (for backend designer).
  3. Participate in chip debug, validation, and marketing specifications.
 
Qualifications:
 
  1. BSEE with minimum 3-year experience or MSEE with minimum 1-year experience of digital experience.
  2. Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication), timing analysis, DFT, meta-stability, etc.
  3. Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, and decimation.
  4. Desired usage experience of mainsteam industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
  5. Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
  6. Experience in bus design (I2C, AHB/APB/AXI), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
  7. Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
  8. Experience in mixed-signal SOC design is a plus.
  9. Experience in perl/python/tcl scripts is a plus.
 

职位发布者

Photonic HR

7天

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