DFT Engineer

Candidate will be responsible for DFT architecture and test methodology definition, and driving implementation, primarily for Scan-based (ATPG) testing of 77GHz Radar SoCs.

Responsibilities:
- Responsible for DFT planning at IP or fullchip level.
- Responsible for DFT implementation and verification for MBIST.
- Responsible for DFT implementation and verification for Scan/LBIST/ATPG.
- Responsible for DFT design/verification for Clock/JTAG/Analog/DFT IP etc.
- Responsible for DFT pattern generation, release and ATE bringup.
- Responsible for DFT design/flow improvements.

Minimum Requirement:
- BSEE required, MSEE preferred.
- 2~8 years of experience in DFT field.
- Familiar with Cadence flow.
- Strong logic Design and verification background with experience in STA.
- Must possess a strong knowledge of DFT including scan, ATPG, Test Compression, JTAG and BIST.
- Programming in Perl, tcl and C/C++ is a plus.
- Good English communication skills.
- Self-motivated and good team player.