Senior/Staff Verification Engineer

Job Responsibilities:
The senior logic verification engineer works on simulation-based functional verification for subsystem. He works with global team to increase the quality of design, ensures the functional correctness with specified performance and power. His major tasks includes verification plan creation, test environment setup, test case developing, simulation debug, and verification signoff.
Responsibility:
* Subsystem function and verification requirement understanding * NBIO level test plan, test bench, testcase development
* Metric driven simulation, regression triage, and signoff
* Technical consult support to SOC teams

Job Requirements:

1. Candidate is preferred to be MSEE with a bout of 3 years or BSEE with 5 years’ experience in digital ASIC/SOC design verification.
2. Direct experience on Complex IP/ASIC/SOC Design Verification is preferred
3. Good understanding on logic verification with skill on HDL language and verification
   methodology
4. Object-oriented programming, SystemVerilog and UVM verification skills are preferred
5. Understanding of high speed IO standard (PCI-e, HT, USB, DDR, DisplayPort) is a plus.
6. Experience of verification of large scale ASICs with random/assertion based techniques,
   power aware simulation, formal verification is a plus
7. Strong C and C++ software development and scripting languages experience is a plus (Perl,C Shell, Makefile and etc).
8. Good communication on native language and English