Senior DV Engineer

Responsibility:
Participate in mix-signal IC product development, including design and verification. Contribute to verification platform and write and review validation test plans.

Requirement:
 Experience on RTL related verification.
 Experience on System Verilog and UVM is preferred.  Experience on perl/tcl scripts and make-file is preferred.  Good spoken and written English
 Good team work and communication skills

Qualification:
 MSEE or related
 3~5 years related working experiences