Verification Engineer

1. Position Title:    Verification Engineer
JDiscription: 
1. Responsible for advanced verification methodology development for IP verification
2. Responsible for TOP level verification planning, behavioral modeling, system level verification environment setup, test case development and regressions
3. Mixed signal simulation
4. Co-work with IP teams on IP verification
5. Co-work with  team on silicon validation and issue debug
Qualification Requirement
1. master /bachelor degree in microelectronic circuit or systems
2. At least 5 years’ experience in product’s verification position
3. Experience in FPGA, automotive Battery manager system is a plus
4. Experience in mixed signal simulation and familiar with CADENCE AMS tool is a plus.
5. Skilled in scripting language, such as TCL, Perl, C shell, Makefile
6. Good communication skill  
7. Good knowledge of the English language (both written and verbal)