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北京华芯通半导体技术有限公司

Staff Engineer, PCIE IP Design

收藏职位
  • 我要分享
  • 30万-60万/年
  • 上海
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 五险一金,福利好,老板nice,技术领先,成长空间大

发布时间: 2018-12-26发布

职位描述

Position Description
Design PCIE controller, including specification, architecture, micro-architecture, implementation (using Verilog), and verification
 
 
Responsibilities
Join PCIE design team, take responsible of Best In Class PCIE controller design, target for low high performance, low cost and low power architecture exploration and IC implementation.
 
Qualifications
5+ years IC industry, 2+ years PCIE dedicate experience
Master or above in EE is a plus
 
 
Skills and Knowledge
Programming skills in Verilog HDL
Must be familiar with all stages of the ASIC design flow (including specification,
Must be familiar with PCIE protocol and industry experience on RC/EP controller design.
architecture, and design implementation)
Highly motivated and skillful at solving difficult technical problems
Knowledge of bus or low-power design techniques is a plus
 
 
 
 
 

职位发布者

刘强

HR

7天

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98%

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