Digital Verification Engineer

Team Introduction:
ADI’s Audio Image Sensing Group is focused on the state of the art audio, image and photoelectric mixed signal IC development for healthcare consumer products. The team competences include architecture and signal chain analysis, analog model design and integration, algorithm development, digital logic design, implementation and functional/mix signal verification. We are looking for a highly motivated individual to join our team and improve our verification discipline. The successful candidate will be able to learn and contribute to the cutting edge technology of Vital Sens Monitor in wearable consumers, Time of Flight technology in 3D image sensing, and Acoustic Noise Cancellation in high-end audio productions.  This is a great opportunity for someone is ready to expand on their verification skills and also contribute to a wider spectrum of digital + analog design practices.
 
Responsibility:
•             Lead the in verification team
•             Define functional verification and mix-signal verification methodology.
•             Develop verification plan and arrange reviews with system, digital, analog, and validation engineers. Develop test-benches, driving for functional/structural coverage closure
•             Synergies UVM and legacy verification environments to fulfill the schedule and quality requirements
•             Perform chip-level integration verification as well as sub-system and module level verification
•             Develop assertions and cover-groups that align with verification plan
•             Define methods to do performance verification of digital signal processing DUTs and signal chain sub-systems
•             Team work with digital and analog design engineers to define gate level simulation and co-sim environment.
•             Developing system level tests for functional validation and stress test
•             Working on pre-silicon FPGA validation, System-C emulation activities to augment simulation verification
•             Involvement in post-silicon activities such as silicon bring-up, evaluation support, ATE pattern bring-up to take SoC into production
•             Successfully communicate with designers of multiple product types to deliver first-pass success silicon
 
Requirement:
•             MSEE or PhD in EE or related
•             5-8 years of professional experience
•             Experience in UVM and SystemVerilog
•             Experience with Cadence tools
•             Experience in mixed-signal verification is preferred
•             Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage
•             Experience in power-aware simulations and debug is a big plus
•             Experience in formal verification tools is a plus
•             Experience in scripting languages such as  Perl and TCL is a plus
•             Must have exceptional interpersonal and communication skills
•             Must be a self-starter, should be able to work on assignments with minimal directions