资深数字设计工程师/Senior ASIC Design Engineer（薪资面议）

Job description

• Be responsible for the development of digital circuit design in SoC or Mixed Signal products.
• Define internal design spec basing on marketing datasheet
• Responsible for RTL design & simulation, logic synthesis, static timing analysis, formal check and DFT.
• Support FPGA verification
• Support product test and debug after sample release.

• Bachelor degree or above in EE
• Minimum 3 years ASIC logic design experience
• Familiar with HDL design with Verilog or VHDL
• Familiar with ASIC/SoC design and verification flow
• Familiar with scripts of TCL, Perl, etc. is a plus.
• Familiar with Place & Routing flow is a plus.
• A successful product development from specification to GDSII experience is a plus
• Good communication skills and teamwork
• It will be a big plus if relative experience on one or more of FIR, Driver, Smartcard and RFID.

• 负责SoC或混合信号芯片中数字电路的RTL设计开发工作
• 负责设计文档的撰写
• 负责逻辑综合，静态时序分析，一致性验证等
• 参与测试和仿真向量生成，FPGA相关验证支持
• 参与芯片的样品调试和量产测试.

• 硕士学历，电子工程，微电子，或相关专业
• 3年以上数字电路设计经验
• 熟悉ASIC 流程，熟悉VHDL/Verilog
• 具有数字、模拟电路的基础知识，学习能力强；
• 良好的沟通能力及团队合作精神
• 有成功产品完整开发和流片经历
• 优先考虑有以下相关经验之一：滤波器，Driver, 智能卡或RFID.