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ASIC Logic Design Engineers (Senior and entry levels)

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  • 我要分享
  • 13万-26万/年
  • 天津
  • |
  • 工作经验不限
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 股票期权,年终奖金,五险一金,福利好,年底双薪,年度旅游,技术领先,成长空间大,节日礼物,老板nice

发布时间: 2021-09-14发布

职位描述


Functions: 
·           Develop micro-architecture based on specification and customer input. 
·           Develop implementation spec for sub-blocks. 
·           Verilog design, DFT and timing closure. 
·           Block level verification and FPGA prototyping.  
Requirements: 
·           Solid knowledge of semiconductor logic design and flow, familiar with Synthesis and Static Timing Analysis.  
·           Strong programming skills (C/C++/SystemC/Verilog). 
·           Familiar with UNIX environment Perl/ TCL/bash/csh. 

·           Strong analytical and problem solving capability. 
·           Good communication skills and presentation skills, easy to work with. 
·           Detail oriented, methodical. 
·           Able to read and interpret English specifications and documents accurately. 
·           BS, MS or Ph.D. degree in Computer Science or Electrical Engineering.
 
 
 
 

职位发布者

norelsys

HR

7天

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