Digital Design Verification Engineer
- 15万-22万/年
- 北京
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- 应届生/在校生
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- 硕士
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- 全职
职位诱惑: 年终奖金,五险一金,福利好,成长空间大
发布时间: 2018-03-26发布
职位描述
Participate in mix-signal IC product design:
Chip/block level RTL design and implementation.
Design FIR/IIR and signal processing blocks from algorithm, convert Algorithms to digital design.
Architecture definition according to product spec.
Participate in block and chip level verification:
Modeling/simulating/debugging digital circuit with Verilog/system Verilog/UVM or C++
Participate in block/system level digital/mix-signal testbench development
Making verification plan, creating test cases and analyzing test results
Requirement:
MSEE or PhD in Microelectronics/Electrical Engineering or relate.
Self-motivation, result oriented, good team work and communication skills
Excellent problem solving skill
Knowledge with digital signal processing and Matlab skills is a plus.
Scripts (perl, tcl, c shell) skill is a plus.
Digital implementation experience is a plus.
Good initiative and motivation in a challenging environment
Good spoken and written English