Senior Analog IC Layout Engineer

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21万-28万/年
北京
|
3年以上
|
本科
|
全职

职位诱惑: 年终奖金,五险一金,老板nice,年底双薪,股票期权,年度旅游,技术领先,成长空间大,技能培训,福利好,天天下午茶,节日礼物

发布时间: 2018-05-08发布

职位描述

Principal Duties and Responsibilities:
Design the analog layout in power management products. Design includes low & high voltage CMOS layout design and DRC, LVS verification.
Finish analog IC top layout and DRC, LVS verification independently.

Knowledge, Skills, and Abilities Required:
? BSEE with knowledge in analog IC layout design.
? Preferably with 3 to 5 years working experience in CMOS process
? Good knowledge in design of IC analog top and block layout.
?? Able to work in a team with good written and communication skills.
? Able to finish project layout independently.
? Preferably with high voltage BCD process experience.