BIST Logic Design Engineer

BIST Logic Design Engineer
Location: Shanghai
Responsibilities:
BIST Logic Engineer is working on cutting-edge Memory IP BIST
development. By employing the industry leading tools, state of the art methodology, and
innovative semiconductor leading technologies from 14nm and beyond, you will be
participating in the BIST design and verification, including architecture definition, logic design,
and block and system level module verification.
Requirements:
1. ME/EE/CS or background in related areas.
2. Skilled in RTL logic design (Verilog and/or VHDL), research and/or development skill in one
or more of the following area is preferable: BIST, ATPG, DFT, UVM Verification.
3. Proficiency in programming and/or scripting languages.
4. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible
and dynamic environment.
5. Good English skills, communication skills, and willingness to work with a global team.