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上海芯海集成电路设计有限公司

BIST Logic Design Engineer

收藏职位
  • 我要分享
  • 25万-40万/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,年底双薪,年度旅游,技术领先,成长空间大,节日礼物,技能培训

发布时间: 2018-03-27发布

职位描述

BIST Logic Design Engineer
Location: Shanghai
Responsibilities:
BIST Logic Engineer is working on cutting-edge Memory IP BIST
development. By employing the industry leading tools, state of the art methodology, and
innovative semiconductor leading technologies from 14nm and beyond, you will be
participating in the BIST design and verification, including architecture definition, logic design,
and block and system level module verification.
Requirements:
1. ME/EE/CS or background in related areas.
2. Skilled in RTL logic design (Verilog and/or VHDL), research and/or development skill in one
or more of the following area is preferable: BIST, ATPG, DFT, UVM Verification.
3. Proficiency in programming and/or scripting languages.
4. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible
and dynamic environment.
5. Good English skills, communication skills, and willingness to work with a global team.

职位发布者

Jessy

Account Manager

7天

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