Physical Design Engineer

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12万-20万/年
上海
|
应届生/在校生
|
硕士
|
全职

职位诱惑: 年终奖金,五险一金,老板nice,股票期权,技术领先,成长空间大

发布时间: 2019-07-05发布

职位描述

Job Description:

Handle all aspects of chip backend design, including floor planning, place and routing, CTS, timing convergence iterations/optimization, DFT and final DRC/LVS.

Qualifications:

1.Experience with Synopsys and/or Cadence design tools.
2.Familiar with 45/40nm or lower CMOS process designs.
3.Having successful tape out experience will be a great plus.
4.Good communication skills, team spirit and be anxious to learn during daily work.