Physical Design Engineer
Handle all aspects of chip backend design, including floor planning, place and routing, CTS, timing convergence iterations/optimization, DFT and final DRC/LVS.
1.Experience with Synopsys and/or Cadence design tools.
2.Familiar with 45/40nm or lower CMOS process designs.
3.Having successful tape out experience will be a great plus.
4.Good communication skills, team spirit and be anxious to learn during daily work.