哎呀,这个职位已经下线啦
澜起科技(上海)有限公司
Analog Design Engineer (2018届应届生)
- 15万-30万/年
- 上海
- |
- 应届生/在校生
- |
- 硕士
- |
- 全职
职位诱惑: 十五薪,老板nice,年度旅游,成长空间大,技术领先,技能培训
发布时间: 2017-09-12发布
职位描述
JOB DESCRIPTION:
- Design, evaluate and verify high speed CMOS analog/mixed circuits;
- Work closely with layout engineer for layout implementation;
- Engineering lab test and chip debug;
- Technical documentation for design, lab test, circuit analysis.
QUALIFICATION:
- MS in electric and electronic engineering;
- Good fundamental in design and analysis of analog/mixed circuit;
- Good understanding in CMOS process technology and device physics;
- Experience in behavioral modeling by Verilog and/or Matlab;
- Familiar with EDA tools (Virtuoso, spectre, HSPICE, calibre, etc);
- Design experience in any of the following areas is preferred: SerDes, high-speed I/O’s, PHY, PCIe, USB.
职位发布者
周超
7天
简历处理用时
74%