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Cadence

Senior / Principal Design Engineer (数字前端设计)

  • 32万-55万/年
  • 北京
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,股票期权

发布时间: 2018-01-07发布

职位描述

Position Description:
Deliver/implement HBM IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.
 
Specific duties include:
- Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow
 
- Proficiency in logic design, simulation, synthesis, STA and testing
- Proficiency in Verilog and its simulation environment
- Good knowledge of IC design
 
* At least five years experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
 
Position Requirements:
1. Essential Qualifications: Must have BS degree with 6+ years of applicable experience, MS degree with 4+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written. 3. Requires good communication skills in English.

职位发布者

Cencily Chen

Sr.Manager&BP

6天

简历处理用时

99%

简历及时处理率