ASIC Logic Verification Engineers

专业要求：
1． Analog and Mixed signal IC custom layout design.
2. Chip/Top level floorplanning and integration (Senior layout engineer).
职位描述：
1.Familiar with verification methodology and IC design and verification flow
2.Good knowledge of  Verilog/C/C++/System C/SystemVerilog.
3.Fluent in UNIX script programming (Perl/ TCL/bash/csh)
4.Experienced with simulation tools
5.Extensive RTL development experience (Verilog or VHDL) is a plus.
6.Experienced in IP based verification/integration and common peripherals in SOC is a plus
7.Good communication skills and presentation skills, easy to work with.
8.Fluent in English. Able to read, write and interpret English specifications and documents accurately.
9. BS, MS or Ph.D. degree in Computer Science or Electrical Engineering