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北京华芯通半导体技术有限公司

Design Implementation Engineer (2018 Fresh Graduate)

  • 10万-20万/年
  • 北京
  • |
  • 应届生/在校生
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice

发布时间: 2018-12-26发布

职位描述

Job Title: Design Implementation Engineer (2018 Fresh Graduate)
 
Location: Beijing/Shanghai
 
Responsibilities
- Responsible for digital logic synthesis, STA, formal verification and low power check
- Responsible to develop timing constraint and low power design constraint
- Responsible to co-work with physical design team for timing closure
- Responsible to optimize digital frontend flow qualification
 
Qualifications
Education and Experience
- Major in CS, EE or related, MSEE required
 
Skills and Knowledge
- Good knowledge of digital logic design, synthesis, STA, formal verification, etc.
- Good experience with Design compiler, Prime time and Formality/Conformal LEC
- Knowledge of DFT or physical design is a plus
- Familiar with common UNIX utility such as Shell, Perl, TCL
- Good English communication skills
- Self-motivated and good team player

职位发布者

刘强

HR

7天

简历处理用时

98%

简历及时处理率